1. Field of the Invention
The invention relates to a buffer circuit using a low electric-current-consumption-type operational amplifier and to a driver IC having many buffer circuits.
2. Description of the Related Art
In many cases, a buffer circuit using an operational amplifier is used for a driver IC for use with a source drive provided in a liquid-crystal display device (LCD) or an organic EL display device. In accordance with an increase in the size of a display panel, demand exists for a driver IC with a buffer circuit which achieves large-capacity drive capability, a decrease in power consumption, and a high-speed output response. An output voltage of the driver IC must be controlled over a wide range from a ground potential to levels in the vicinity of a source potential.
FIG. 6 is a view showing the configuration of a related-art operational amplifier 500 of rail-to-rail type such as disclosed in IEICE transactions, 2001/5 Vol. J84-C No. 5 pg. 364 FIG. 15. FIG. 7 shows a buffer circuit formed by connecting an output voltage Vout of the operational amplifier 500 directly to an inverted input terminal (−) thereof, thus constituting a buffer circuit and driving a load capacitor Co. FIGS. 8A and 8B show time characteristics of input and output voltages in the buffer circuit shown in FIG. 7.
In FIG. 6, reference numerals 501 to 510 designate MOSFETs, and MOSFETs whose gates are given circles are p-type MOSFETs (hereinafter abbreviated as “PMOS transistors”). The remaining MOSFETs are n-type MOSFETs (hereinafter abbreviated as “NMOS transistors”). Reference numerals 511 to 514 designate constant current sources for causing electric currents Iss1 to Iss4 to flow. Reference numerals Vb51 to Vb53 denote bias voltages.
The related-art buffer circuit employs a PMOS transistor and an NMOS transistor as input terminals. When the input voltage Vinp is considerably low, the NMOS transistors 501, 502 are brought into a cut-off state, whereby the electric current Iss2 assumes a value of zero. Hence, the input transistor is actuated by means of only the PMOS transistors 509, 510. In contrast, when the input voltage Vinp is considerably high, the PMOS transistors 509, 510 enter a cut-off state, and the electric current Iss1 assumes a value of 0. Therefore, the input transistors are actuated by means of only the NMOS transistors 501, 502. When the input voltage Vinp falls within the remaining range outside these ranges, both input transistors; that is, the PMOS transistors 509, 510 and the NMOS transistors 501, 502, operate. In this way, the input transistors can operate at the input voltage Vinp in the full range (i.e., a rail-to-rail range) from the ground potential Vss to the source potential Vdd, by means of the related-art buffer circuit.
In order to achieve a reduction in power consumption, the related-art buffer circuit must reduce current values Iss1 to Iss4 of constant current sources 511 to 514. Particularly, when battery cells are used as the power source as in the case of a portable device, a reduction in power consumption is an important consideration.
In a case where the load capacitor Co is activated by means of a related-art buffer circuit, when the input voltage Vinp has changed in a rectangular pattern between a voltage V1 and a voltage V2, as can be seen from a time characteristic chart of the input voltage shown in FIG. 8A and a time characteristic chart of the output voltage shown in FIG. 8B, the output voltage Vout requires consumption of a rise time T1 from the voltage V1 to the voltage V2 and consumption of a fall time T2 from the voltage V2 to the voltage V1. The times T1, T2 are dependent on a decline α determined by a ratio of the electrostatic capacity of the load capacitor Co to the current value Iss4 of the constant current source 514.
The electrostatic capacitance of the load capacitor Co is determined by a display panel to be driven by the buffer circuit. When the current value of the constant current source is reduced for reducing power consumption, a limitation is imposed on the driving capability of the buffer circuit, and hence the rise and fall of the output voltage involve consumption of a time, thereby posing difficulty in realization of a high-speed output response. An attempt to realize high-speed output response can be made by increasing the current value of the constant current source. However, in this case a large current is caused to flow at all times, which in turn results in an increase in power consumption. A reduction in power consumption and large-capacity driving capability and the high-speed output response are competing objectives, and difficulty is encountered in attaining both improvements.